Skills

  • 10 years+ experience in CPU micro-architecture and logic design
  • Experiences of modern processor core design, especially x86 core
  • Skills in Verilog/System Verilog
  • Skills in Python, Perl, and C/C++
  • Skill in FPGA prototyping
  • Experiences of silicon bring up and debug methodology
  • Knowledge about RISC-V ISA

Work Experience

  • 2013-Now, Beijing Zhaoxin Semiconductor Co., Ltd. CPU Micro-architecture Engineer
  • 2009-2013, VIA Technologies, Inc. CPU Logic Engineer

Projects

x86 Soc for Desktop and Ultra-book KX-7000

  • Project Duration: 2019.2 - Now
  • Project Description: New x86 SoC with 15-90W TDP, for desktop and ultra-book
  • Responsibility:
    • Define power management feature including C-state, P-state, Turbo Boost, Thermal Management, RAPL, HWP etc.
    • Improve power model feature on c-model
    • Define and implement a new RISC-V MCU as main power control unit(PCU)
    • Define PCU behavior spec and implement with design team members (both hardware and firmware)
    • Co-work with GPU team, for total power budget sharing within TDP

16nm x86 SoC for Ultra-book KX-6000G

  • Project Duration: 2018.2 - 2022.3
  • Project Description: New x86 SoC with 15-35W TDP
  • Responsibility:
    • Define power management feature including C-state, P-state, Turbo Boost, RAPL, HWP etc.
    • Implement power model feature on c-model
    • Define PCU spec and implement with design team members (both hardwrare and firmware)
    • Co-work with GPU team, for total power budget sharing within TDP

16nm x86 SoC KX-6000

  • Project Duration: 2017.2 - Now
  • Project Description: A new generation 16nm x86 SoC
  • Responsibility:
    • Debug methodology for post-silicon debug
    • Regression website base on Jenkins
    • Silicon debug support CV team

28nm x86 SoC KX-5000

  • Project Duration: 2015.10 - 2016.12
  • Project Description: A new generation 28nm x86 SOC: KX-5000, mess production
  • Responsibility:
    • Debug methodology for post-silicon debug
    • Regression website base on Jenkins
    • Silicon debug support CV team

28nm x86 CPU, ZX-C

  • Project Duration: 2013.1 - 2015.10
  • Project Description: A new generation 28nm x86 CPU core,
  • Responsibility:
    • Frontend pipeline improvement, add AVX2 support
    • Define new marco-op to achieve high IPL for CPU core
    • Micro-code for C-state and P-state
    • Develop a new debug methodology for post-silicon debug

Freshmen Training Program

  • Project Duration: 2012.8 - 2012.10
  • Project Description: Training program for first year employees
  • Responsibility: Develop a 5-stage single issue CPU project called Y86 for freshmen training program. Help freshmen understand basic knowledge of CPU and ASIC design

x86 CPU Prototyping on FPGA

  • Project Duration: 2010.3 - 2012.5
  • Project Description: Prototyping a new version CPU on FPGA， Guarantee functional correct of design
  • Responsibility:
    • Setup a one-click toolchain to transform ASIC design in FPGA design, including clock tree, reset tree, ASIC IP, interconnection between FPGAs
    • Bring up two generation CPU on this FPGA prototyping platform

x86 CPU FSB Capturer

  • Project Duration: 2009.12 - 2010.2
  • Project Description: FSB Capturer(FSBC) is a special logic analyzer for x86 CPU’s bus interface
  • Responsibility: Design FSBC on a V5 FPGA, and bring up the whole new bus debug flow